1. Field of the Invention
This invention relates in general to macrocell arrays and, more particularly, to a multi-gate bipolar macrocell array having an on-chip clock generator.
2. Background Art
To satisfy the demand for large scale digital integrated circuits, the semiconductor industry has developed three basic approaches. These include standard, off the shelf circuits; custom circuits; and gate arrays. The standard, off the shelf circuit provides the lowest cost option due to the quantities manufactured, but are limited in providing the flexibility for the circuit desired. The custom circuit is cost limiting unless the number of circuits desired is large. The gate array involves a standard array of a large number of gate circuits diffused into a chip. The metallization pattern converting these gate circuits into functional custom circuits is processed according to the customer's requirement.
A macrocell array is an extension of the gate array concept. A macrocell is an array subsection performing a higher level logic function than a basic gate. A macrocell array is an array circuit in which macro functions used to define logic simulations are directly implemented within the basic cell structure rather than formed by interconnecting logic gates. Each cell in a macrocell array contains a number of unconnected transistors and resistors. A metallization interconnecting pattern transforms the interconnected transistors and resistors within each cell into Small Scale Integrated (SSI) logic functions, called macros. The macros take the form of standard logic elements such as dual type "D" flip-flops, dual full adders, quad latches, and many other predefined functions. The macros are also interconnected by the metallization to form the desired Large Scale Integrated (LSI) design. The high density packing of a macrocell array chip offers up to a fifty to one reduction in system component count, with a power dissipation improvement of as much as five to one.
A typical macrocell array has input cells for receiving an input and for logic functions, output cells for providing an output and for logic functions, major cells for receiving an input and for logic functions, bias generator cells providing bias voltages, and clock generator cells for providing clock pulses. Only the bias generator cells would not be connected to an input/output pad.
However, the previously known macrocell arrays have drawbacks that have presented problems for both the designer and the end user. Clock generators used to clock the gates of a macrocell array typically have a narrow pulse. A clock pulse typically has a large fan-out; that is, it must drive a large number of gates. This large fan-out causes the narrow pulse to shrink. If the magnitude of the pulse shrinkage is too great, the pulse will become so narrow as to cause improper circuit operation. Additional pulse width problems arise because some chips are slower than others, and the slower chips require a wider pulse.
Thus, what is needed is a macrocell array having an on-chip clock generator having a narrow pulse with reduced sensitivity to large fan-out.